1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly to methods and apparatuses for high speed addressable buffers for selecting addresses in memory devices.
2. Description of the Related Art
As is well known in the art, memory devices are generally array structures composed of 2.sup.n by 2.sup.m individual memory cells which are coupled to wordlines (rows) and complementary pair bit lines (columns). A typical memory cell may be composed of transistors coupled together to form a data storage device. An individual memory cell is typically selected when an X-decoder is used to select rows and a Y-decoder is used to select columns. A synchronous memory device utilizes a system clock S.sub.CLK to generate a clock signal S.sub.CLK to enable a selected address location to drive an output node to a state consistent with data stored in the selected memory cell location. As is well known in the art, in any synchronous memory device, the time delay between a falling edge or a rising edge of a clock signal S.sub.CLK and the true selected data available at the output node is a critically important performance parameter.
FIG. 1A is a block diagram illustrating conventional methods for selecting a specific wordline (i.e., W.sub.1 . . . W.sub.N) from a core 100 in a synchronous memory device. In typical synchronous architectures, computers access memory core 100 through an address input bus 110 that may be coupled to a conventional X-decode address selector 102a, which is coupled to an X-decode buffer 102b, and a Y-decode address buffer (not shown). For ease of understanding, the Y-decode address buffer will not be described, however, the principles and concepts are generally applicable to all conventional addressable buffer configurations.
Typically, X-decode address selector 102a presents a pre-selected wordline address to the X-decode buffer 102b when signal clock S.sub.CLK makes a transition. By way of example, when clock signal S.sub.CLK transitions from either LOW to HIGH, or HIGH to LOW, the selected wordline is able to drive output 103 to a logical state consistent with digital data stored in the selected memory cell location. In other words, when a read operation is performed, a specific wordline address is decoded by the X-decode address selector 102a (once a Y address has already been selected), and presented to the X-decode buffer 102b. Once the clock signal S.sub.CLK produces a rising edge, the X-decode buffer 102b is triggered, thereby enabling the selected wordline to drive output 103 to a logic state consistent with digital data stored in the selected memory core cell location.
Unfortunately, the above-described X-decode buffer configuration may have slow data access times that may be unsuitable for speed sensitive applications. That is, typical X-decode buffer configurations introduce speed reducing propagation delays as well as high input capacitances that detrimentally impact clock signal S.sub.CLK drivers. Because data access times are typically measured in terms of the rise or fall times experienced by the clock signal S.sub.CLK, it is advantageous to reduce the input capacitance as well as reducing propagation delays. Unfortunately, typical X-decode buffers tend to introduce clock signal S.sub.CLK input capacitances that are up to about 30 pF and propagation delays that are approximately equivalent up to about 5 gate delays or more.
FIGS. 1B and 1C illustrate exemplary prior art attempts at decreasing data access times in synchronous memory devices. FIG. 1B illustrates a prior art attempt at reducing synchronous memory data access times by reducing clock input capacitance. In this example, the size of an input driver (I1) is decreased to reduce the input capacitance experienced by clock signal S.sub.CLK. Unfortunately, reducing the size of input driver (I1) necessarily reduces its drive capacity which in turn necessitates an offsetting increase in the number of inverter stages INV.sub.N (where N is even).
In other words, because the input driver (I1) is reduced in strength, a plurality of delay producing inverters must be incorporated to produce a drive strength that is sufficient to drive an output buffer (B1). As such, the increased number of inverter stages (INV.sub.N), adds gate delays to the overall data access time of the synchronous memory device. As a side effect, the increased delays cancel out the enhancements in speed associated with the reduction in clock input capacitance.
FIG. 1C illustrates another prior art attempt at reducing access times in synchronous memory devices. In this configuration, the inverter stages of FIG. 1B are eliminated, which beneficially provides a reduction in access delays. However, removing the inverter stages requires that substantially all of the drive current for output driver (B2) be supplied by the input driver (I2). As a result, the high drive input driver (I2) will generate a large input capacitance for clock signal S.sub.CLK, thereby erasing any benefit provided by having less gate delays.
Unfortunately, in applications using synchronous memory devices where data access times are of critical importance, the slow response of X-decode buffers may disadvantageously limit a system's overall performance. For example, although Central Processing Unit (CPU) system clock speeds have continually increased in recent years, memory access operations are a necessity when performing data reads from memory. As can be appreciated, the slowest operation in a CPU/memory interface will ultimately determine a system's overall processing performance. It is thus important that delays associated with performing memory access operations be reduced to prevent more global system delays.
In view of the foregoing, there is a need for methods and apparatuses for providing high speed memory access circuitry. In particular, there is a need for addressable high speed buffer circuitry that enables memory access operations to occur at higher speeds.